HD6417751 Datasheet, PDF (864/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 22.6 Memory Space Base Address Register (BASE0)
PCILSR0 [28:20]
Register Value
b'0_0000_0000
b'0_0000_0001
b'0_0000_0011
:
b'0_1111_1111
b'1_1111_1111
Required Address
Space
1 MB
2 MB
4 MB
:
256 MB
512 MB
BASE0[31:20]
Valid Writable Bits
Bits 31 to 20
Bits 31 to 21
Bits 31 to 22
:
Bits 31 to 28
Bits 31 to 29
The PCICONF5 register is initialized to H'00000000 at a power-on reset and software reset.
Always write to this register before transferring data to and from the PCIC memory from the PCI
bus.
Bits 31 to 20—Base Address of the Memory Space 0 (BASE0 31 to 20): These bits specify the
base address of the local address space 0 (SH7751 Series external bus space).
Bits 19 to 4—Base Address of the Memory Space 0 (BASE0 19 to 4): Fixed at H'0000 in
hardware.
Bit 3—Pre-fetch Control (LA0PREF): Shows availability of prefetching of the local address
space 0.
Bit 3: LA0PREF
0
1
Description
Prefetch disabled
Prefetch enabled (not supported)
(Initial value)
Bits 2 and 1—LA0TYPE1 and 0: In the case of I/O space, can be set as the base address. Shows
the memory type of the local address space 0.
Bit 2: LA0TYPE1
0
1
Bit 1: LA0TYPE0
0
1
0
1
Description
Base address can be set to 32-bit width, 32-bit space
(Initial value)
Base address can be set to 32-bit width, less than
1MB space (not supported)
Base address is 64-bit width (not supported)
Reserved
Rev. 3.0, 04/02, page 824 of 1064