HD6417751 Datasheet, PDF (503/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Section 14 Direct Memory Access Controller (DMAC)
14.1 Overview
The SH7751 Series includes an on-chip four-channel direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed data transfers among external
devices equipped with DACK (DMA transfer end notification), external memories, memory-
mapped external devices, and on-chip peripheral modules (TMU, RTC, SCI, SCIF, CPG, and
INTC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of
the chip. When using the SH7751R, see section 14.6, Configuration of the DMAC (SH7751R),
section 14.7, Register Descriptions (SH7751R), and section 14.8, Operation (SH7751R).
14.1.1 Features
The DMAC has the following features.
• Four channels (SH7751), eight channels (SH7751R)
• Physical address space
• Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum of 16 M (16,777,216) transfers
• Choice of single or dual address mode
 Single address mode: Either the transfer source or the transfer destination (external device)
is accessed by a DACK signal while the other is accessed by address. One data transfer is
completed in one bus cycle.
 Dual address mode: Both the transfer source and transfer destination are accessed by
address. Values set in DMAC internal registers indicate the accessed address for both the
transfer source and the transfer destination. Two bus cycles are required for one data
transfer.
• Choice of bus mode: cycle steal mode or burst mode
• Two types of DMAC channel priority ranking:
 Fixed priority mode: Channel priorities are permanently fixed.
 Round robin mode: Sets the lowest priority for the channel that last received an execution
request.
• An interrupt request can be sent to the CPU on completion of the specified number of
transfers.
Rev. 3.0, 04/02, page 463 of 1064