HD6417751 Datasheet, PDF (964/1105 Pages) Renesas Technology Corp – SuperH RISC engine

(PCIPINT) and PCI power management interrupt mask register (PCIPINTM). Of the power
management interrupts, the power state D3 (PWRS_D3) interrupt detects a transition from the
power state D0 to D3, while power state D0 (PWRS_D0) interrupt detects a transition from the
power state D3 to D0. Interrupt masks can be set for each interrupt.
No power state D0 interrupt is generated at a power-on reset.
The following cautions should be noted when the PCIC is operating in non-host mode and a power
down interrupt is received from the host:
In PCI power management (version 1.0 compatible), the PCI bus clock stops within a minimum of
16 clocks after the host device has instructed a transition to power state D3. After detecting a
power state D3 (power down) interrupt, do not, therefore, attempt to read or write to local registers
that can be accessed from the CPU and PCI bus. Because these registers operate using the PCI bus
clock, the read/write cycle for these registers will not be completed if the clock stops.
22.9.2 Stopping the Clock
Power savings can be achieved by stopping the bus clock used by the PCIC and the PCI bus clock.
The PCI clock control register (PCICLKR) is provided for controlling the PCIC clock. Regarding
the control register for stopping the peripheral module clock (PCLK) in the PCIC, refer to section
9, Power-Down Modes.
The method of stopping the clock differs according to the operating mode of the PCI bus clock.
See table 22.14.
Rev. 3.0, 04/02, page 924 of 1064