HD6417751 Datasheet, PDF (461/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
T1 Tw Twe TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.42 Burst ROM Wait Access Timing
CKIO
A25–A5
A4–A0
TS1 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.43 Burst ROM Wait Access Timing
Rev. 3.0, 04/02, page 421 of 1064