HD6417751 Datasheet, PDF (391/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 13: A6PCW1
0
1
Bit 12: A6PCW0
0
1
0
1
Waits Inserted
0 (Initial value)
15
30
50
Bits 11 to 9—Address-OE/WE Assertion Delay (A5TED2–A5TED0): These bits set the delay
time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 11: A5TED2
0
1
Bit 10: A5TED1
0
1
0
1
Bit 9: A5TED0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay
time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 8: A6TED2
0
1
Bit 7: A6TED1
0
1
0
1
Bit 6: A6TED0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Bits 5 to 3—OE/WE Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address
hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Rev. 3.0, 04/02, page 351 of 1064