HD6417751 Datasheet, PDF (363/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM
interface is used in area 5. When burst ROM interface is used, they also specify the number of
accesses in a burst. If area 5 is an MPX interface area, these bits are ignored.
Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: Clear to 0 when PCMCIA interface is set.
Description
Area 5 is accessed as SRAM interface
(Initial value)
Area 5 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
Area 5 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
Area 5 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
Area 5 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
Reserved
Reserved
Reserved
Rev. 3.0, 04/02, page 323 of 1064