HD6417751 Datasheet, PDF (1063/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 23.30 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)
HD6417751RBP240, HD6417751RBP200, HD6417751RF240, HD6417751RF200:
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to 75°C, C_L = 30 pF
Pin
Item
PCICLK
Clock cycle
Clock pulse width (high)
Clock pulse width (low)
Clock rise time
Clock fall time
3&,567
Output data delay time
IDSEL
Input hold time
Input setup time
AD31–AD0 Output data delay time
C/%(–C/%( Tri-state drive delay time
PAR
3&,)5$0(
,5'<
75'<
Tri-state high-impedance
delay time
Input hold time
Input setup time
3&,6723
3&,/2&.
'(96(/
3(55
3&,5(4/
*17,1
3&,5(4/
MD9
3&,5(4/
MD10
3&,5(4/
3&,*17/
5(4287
Output data delay time
Tri-state drive delay time
Tri-state high-impedance
delay time
Input hold time
Input setup time
3&,*17–
3&,*17
6(55
Tri-state drive delay time
,17$
Tri-state high-impedance
delay time
Symbol
t_PCICYC
t_PCIHIGH
t_PCILOW
t_PCIr
t_PCIf
t_PCIVAL
t_PCIH
t_PCISU
t_PCIVAL
t_PCION
t_PCIOFF
33 MHz
Min Max
30 —
11 —
11 —
—
4
—
4
—
10
1.5 —
3
—
—
10
—
10
—
12
t_PCIH
t_PCISU
1.5 —
3
—
66 MHz
Min Max
15
30
6
—
6
—
—
1.5
—
1.5
—
8
1.5 —
3
—
—
8
—
10
—
12
Unit Figure
ns 23.70
ns 23.70
ns 23.70
ns 23.70
ns 23.70
ns 23.71
ns 23.72
ns 23.72
ns 23.71
ns 23.71
ns 23.71
1.5 —
3
—
ns 23.72
ns 23.72
t_PCIVAL
t_PCION
t_PCIOFF
t_PCIH
t_PCISU
—
10
—
10
—
12
1.5 —
3
—
—
8
—
10
12
1.5 —
3
—
ns 23.71
ns 23.71
ns 23.71
ns 23.72
ns 23.72
t_PCION
t_PCIOFF
—
10
—
12
—
10
ns 23.71
—
12
ns 23.71
Rev. 3.0, 04/02, page 1023 of 1064