HD6417751 Datasheet, PDF (621/1105 Pages) Renesas Technology Corp – SuperH RISC engine

15.2.7 Serial Status Register (SCSSR1)
Bit: 7
6
5
4
TDRE RDRF ORER FER
Initial value: 1
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
—
R
0
MPBT
0
R/W
SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI,
and multiprocessor bits.
SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1.
Bit 7: TDRE
0
Description
Valid transmit data has been written to SCTDR1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When data is written to SCTDR1 by the DMAC
1
There is no valid transmit data in SCTDR1
(Initial value)
[Setting conditions]
• Power-on reset, manual reset, standby mode, or module standby
• When the TE bit in SCSCR1 is 0
• When data is transferred from SCTDR1 to SCTSR1 and data can be
written to SCTDR1
Rev. 3.0, 04/02, page 581 of 1064