HD6417751 Datasheet, PDF (89/1105 Pages) Renesas Technology Corp – SuperH RISC engine

From any state when
RESET = 0
From any state when
RESET = 1 and MRESET = 0
Power-on reset state
RESET = 0
Manual reset state
Reset state
RESET = 1
RESET = 1,
MRESET = 1
Exception-handling state
Interrupt
Bus request
Bus request
clearance
Bus-released state
Exception
interrupt
Bus request
Bus
clearance
request
End of exception
transition
processing
Bus request
Bus request
clearance
Program execution state
SLEEP instruction
with STBY bit
cleared
SLEEP instruction
with STBY bit set
Interrupt
Sleep mode
Standby mode
Power-down state
Figure 2.6 Processor State Transitions
2.7 Processor Modes
There are two processor modes: user mode and privileged mode. The processor mode is
determined by the processor mode bit (MD) in the status register (SR). User mode is selected
when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset
state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which
can only be accessed in privileged mode.
Rev. 3.0, 04/02, page 49 of 1064