HD6417751 Datasheet, PDF (299/1105 Pages) Renesas Technology Corp – SuperH RISC engine

10.9.3 Using Watchdog Timer Mode
1. Set the WT/,7 bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and
the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter.
2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode.
3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does
not overflow.
4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and
generates a reset of the type specified by the RSTS bit. The counter then continues counting.
10.9.4 Using Interval Timer Mode
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each
time the counter overflows. This enables interrupts to be generated at fixed intervals.
1. Clear the WT/,7 bit in the WTCSR register to 0, select the count clock with bits CKS2–CKS0,
and set the initial value in the WTCNT counter.
2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and
sends an interval timer interrupt request to INTC. The counter continues counting.
Rev. 3.0, 04/02, page 259 of 1064