HD6417751 Datasheet, PDF (774/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 19.3 ,5/–,5/ Pins and Interrupt Levels
,5/
0
1
,5/
0
1
0
1
,5/
0
1
0
1
0
1
0
1
,5/
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no
transient level on the ,5/ pin change is detected. In standby mode, as the bus clock is stopped,
noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is
not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt handling starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by IRL interrupt
handling.
Pins ,5/–,5/ can be used for four independent interrupt requests by setting the IRLM bit to 1
in the ICR register.
Rev. 3.0, 04/02, page 734 of 1064