HD6417751 Datasheet, PDF (854/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 27: STA
0
1
Description
No transaction termination using target abort by target device (Initial value)
Transaction termination by target abort by target device. Notification by
target device
Bits 26 and 25—'(96(/ Timing Status (DEV1 and 0): These bits indicate the '(96(/
response timing when the PCIC is operating as a target.
Bit 26: DEV1
0
1
Bit 25: DEV0
0
1
0
1
Description
High-speed (not supported)
Medium speed
Low speed (not supported)
Reserved
(Initial value)
Bit 24—Data Parity Status (DPD): Indicates the 3(55 assert operation or the detection of
3(55 when the PCIC is operating as the master. This bit is set only when the parity error response
bit (bit 6) is 1.
Bit 24: DPD
0
1
Description
Data parity not detected
Data parity occurred
(Initial value)
Bit 23—High-Speed Back-To-Back Status (FBBC): Shows whether a high-speed back-to-back
transfer to a different target can be accepted when the PCIC is operating as a target.
Bit 23: FBBC
0
1
Description
The target does not have a high-speed back-to-back transaction function for
use with other targets
The target has a high-speed back-to-back transaction function for use with
other targets
(Initial value)
Bit 22—User Defined Function System (UDF): Shows whether user defined functions are
supported.
Bit 22: UDF
0
1
Description
This device does not support user functions
This device supports user functions
(Initial value)
Bit 21—66 MHz Operating Status (66M): Shows whether 66 MHz operation is supported.
Rev. 3.0, 04/02, page 814 of 1064