HD6417751 Datasheet, PDF (914/1105 Pages) Renesas Technology Corp – SuperH RISC engine

The PCI-BSC does not support mode register setting of synchronous DRAM nor refreshing of
synchronous DRAM or DRAM. These must be executed by the BSC.
Also, do not implement any settings that are not allowed in slave mode in the PCIC-BSC registers.
This is because bit 30: master/slave flag (MASTER) of the PCIBCR1 is fixed Low, regardless of
the value of the external master/slave setting pin (MP7) at a power-on reset, and the PCIC-BSC
therefore is set in slave mode.
In the case of external memory not used for data transfers with the PCI bus, make the same
settings as the corresponding bus state controller register.
These registers are initialized at a power-on reset, but not by a software reset.
Notes: *1 This register is provided only in the SH7751R, not provided in the SH7751.
*2 MPX is supported only in the SH7751R, not supported in the SH7751.
22.2.39 Port Control Register (PCIPCTR)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
— PORT2EN PORT1EN PORT0EN
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 7
6
—
—
Initial value: 0
0
PCI-R/W: —
—
PP Bus-R/W: R
R
Rev. 3.0, 04/02, page 874 of 1064
5
PB2PUP
0
—
R/W
4
PB2IO
0
—
R/W
3
PB1PUP
0
—
R/W
2
PB1IO
0
—
R/W
1
PB0PUP
0
—
R/W
0
PB0IO
0
—
R/W