HD6417751 Datasheet, PDF (892/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 31—PIO Error (MSTPIO): Error occurred in PIO transfer.
Bit 30—DMA0 Error (MSTDMA0): Error occurred in DMA channel 0 transfer.
Bit 29—DMA1 Error (MSTDMA1): Error occurred in DMA channel 1 transfer.
Bit 28—DMA2 Error (MSTDMA2): Error occurred in DMA channel 2 transfer.
Bit 27—DMA3 Error (MSTDMA3): Error occurred in DMA channel 3 transfer.
Bit 26—Target Error (TGT): Error occurred in target read or target write transfer.
Bits 25 to 4—Reserved: These bits are always read as 0.
Bits 3 to 0—Command Log (CMDLOG3 to 0): These bits retain the PCI transfer command
information (value of C/%( line) upon detection of an error. (Initial value is undefined.)
Rev. 3.0, 04/02, page 852 of 1064