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HD6417751 Datasheet, PDF (79/1105 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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2.2.2 General Registers
Figure 2.3 shows the relationship between the processor modes and general registers. The SH7751
Series has twenty-four 32-bit general registers (R0_BANK0âR7_BANK0, R0_BANK1â
R7_BANK1, and R8âR15). However, only 16 of these can be accessed as general registers R0â
R15 in one processor mode. The SH7751 Series has two processor modes, user mode and
privileged mode, in which R0âR7 are assigned as shown below.
⢠R0_BANK0âR7_BANK0
In user mode (SR.MD = 0), R0âR7 are always assigned to R0_BANK0âR7_BANK0.
In privileged mode (SR.MD = 1), R0âR7 are assigned to R0_BANK0âR7_BANK0 only when
SR.RB = 0.
⢠R0_BANK1âR7_BANK1
In user mode, R0_BANK1âR7_BANK1 cannot be accessed.
In privileged mode, R0âR7 are assigned to R0_BANK1âR7_BANK1 only when SR.RB = 1.
Rev. 3.0, 04/02, page 39 of 1064
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