HD6417751 Datasheet, PDF (360/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor
status for control input pins (NMI, ,5/–,5/, %5(4, MD6/,2,6, 6/((3, 5'<). IPUP is
initialized by a power-on reset.
Bit 25: IPUP
0
1
Description
Pull-up resistor is on for control input pins (NMI, ,5/–,5/, %5(4,
MD6/,2,6, 6/((3, 5'<)
(Initial value)
Pull-up resistor is off for control input pins (NMI, ,5/–,5/, %5(4,
MD6/,2,6, 6/((3, 5'<)
Bit 24—Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor
status for control output pins (A[25:0], %6, &6Q, 5', :(Q, &$6Q, RD/:5, 5$6, &($, &(%,
MD5) when high-impedance. OPUP is initialized by a power-on reset.
Bit 24: OPUP
0
1
Description
Pull-up resistor is on for control output pins (A[25:0], %6, &6Q, 5', :(Q,
&$6Q, RD/:5, 5$6, &($, &(%, MD5)
(Initial value)
Pull-up resistor is off for control output pins (A[25:0], %6, &6Q, 5', :(Q,
&$6Q, RD/:5, 5$6, &($, &(%, MD5)
Bit 21—Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 21: A1MBC
0
1
Description
Area 1 SRAM is set to normal mode
Area 1 SRAM is set to byte control mode
(Initial value)
Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 20: A4MBC
0
1
Description
Area 4 SRAM is set to normal mode
Area 4 SRAM is set to byte control mode
(Initial value)
Rev. 3.0, 04/02, page 320 of 1064