HD6417751 Datasheet, PDF (456/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
RD/
D31–D0
CKE
(High)
Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
Changing the Burst Length (SH7751R Only): When synchronous DRAM is connected with the
32-bit memory bus of the SH7751R, a burst length of either 4 or 8 can be selected by the setting of
the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register.
• Burst Read
Figure 13.39 is the timing chart for burst-read operations. For the example shown below, we
assume that two synchronous DRAMs of 512k × 16 bits × 2 banks are connected and are used
with a 32-bit data width and a burst length of 8. Following the Tr cycle, during which an
ACTV command is output, a READA command is issued during cycle Tc1. During the Td1 to
Td8 cycles, the read data are accepted on the rising edges of the external command clock
(CKIO). Tpc is the cycle used to wait for auto-precharging, which is triggered by the READA
command, to be completed in the synchronous DRAM. During this cycle, no new command
that accesses the same bank can be issued. In this LSI, the number of Tpc cycles is determined
Rev. 3.0, 04/02, page 416 of 1064