HD6417751 Datasheet, PDF (361/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 19—BREQ Enable (BREQEN): Indicates whether external requests and bus requests from
PCIC can be accepted. BREQEN is initialized to the external request and bus request from PCIC
acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup.
The bus request from the PCIC is always accepted in a slave mode start up.
Bit 19: BREQEN
0
1
Description
External requests and bus requests from PCIC are not accepted
(Initial value)
External requests and bus requests from PCIC are accepted
Bit 17—Area 1 to 6 MPX Bus Specification (MEMMPX): Sets the MPX interface when areas 1
to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a power-on
reset.
Bit 17: MEMMPX
0
1
Description
SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are
set as SRAM interface (or burst ROM interface)
(Initial value)
MPX interface is selected when areas 1 to 6 are set as SRAM interface (or
burst ROM interface)
Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST): Specifies the priority of
burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released,
refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not
performed until the end of the DMAC’s burst transfer. This bit is initialized at a power-on reset.
Bit 16: DMABST
0
1
Description
DMAC burst mode transfer priority specification OFF
DMAC burst mode transfer priority specification ON
(Initial value)
Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals
(A[25:0], %6, &6Q, RD/:5, &($, &(%) in standby mode.
Bit 15: HIZMEM
0
1
Description
The A[25:0], %6, &6Q, RD/:5, &($, and &(% signals go to high-
impedance (High-Z) in standby mode and when the bus is released
(Initial value)
The A[25:0], %6, &6Q, RD/:5, &($, and &(% signals drive in standby
mode
Rev. 3.0, 04/02, page 321 of 1064