HD6417751 Datasheet, PDF (821/1105 Pages) Renesas Technology Corp – SuperH RISC engine

21.2 Register Descriptions
21.2.1 Instruction Register (SDIR)
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial
state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is
initialized by the 7567 pin or in the TAP Test-Logic-Reset state. When this register is written to
from the H-UDI, writing is possible regardless of the CPU mode. Operation is undefined if a
reserved command is set in this register.
Bit: 15
14
13
12
11
10
9
8
TI7
TI6
TI5
TI4
TI3
TI2
TI1
TI0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bits 15 to 8—Test Instruction Bits (TI7–TI0)
Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9:
TI7 TI6 TI5 TI4 TI3 TI2 TI1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
—
—
—
0
1
1
1
—
—
—
1
0
1
—
—
—
—
1
1
1
1
1
1
1
Other than above
Bit 8:
TI0
0
0
—
—
—
1
Description
EXTEST
SAMPLE/PRELOAD
H-UDI reset negate
H-UDI reset assert
H-UDI interrupt
Bypass mode (Initial value)
Reserved
Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Rev. 3.0, 04/02, page 781 of 1064