HD6417751 Datasheet, PDF (961/1105 Pages) Renesas Technology Corp – SuperH RISC engine

The following are also set in relation to error interrupts: of the PCI configuration register 1
(PCICONF1), the parity error output status (DPE) the system error output status (SSE), the master
abort reception status (RMA), the target abort reception status (RTA), the target abort execution
status (STA) and the data parity status (DPD).
DMA Channel 0 Transfer Termination Interrupt (PCIDMA0): The DMA termination
interrupt status (DMAIS) bit of the DMA control register 0 (PCIDCR0) is set. The interrupt mask
is set by the DMA termination interrupt mask (DMAIM) bit of the same register.
DMA Channel 1 Transfer Termination Interrupt (PCIDMA1): The DMA termination
interrupt status (DMAIS) bit of the DMA control register 1 (PCIDCR1) is set. The interrupt mask
is set by the DMA termination interrupt mask (DMAIM) bit of the same register.
DMA Channel 2 Transfer Termination Interrupt (PCIDMA2): The DMA termination
interrupt status (DMAIS) bit of the DMA control register 2 (PCIDCR2) is set. The interrupt mask
is set by the DMA termination interrupt mask (DMAIM) bit of the same register.
DMA Channel 3 Transfer Termination Interrupt (PCIDMA3): The DMA termination
interrupt status (DMAIS) bit of the DMA control register 3 (PCIDCR3) is set. The interrupt mask
is set by the DMA termination interrupt mask (DMAIM) bit of the same register.
Power Management Interrupt (Transition Request to Normal Status) (PCIPWON): The
power state D0 (PWRS_D0) bit of the PCI power management interrupt register (PCIPINT) is set.
The power state D0 interrupt mask can be set using the power state D0 (PWRS_D0) bit of the PCI
power management interrupt mask register (PCIPINTM).
Power Management Interrupt (Transition Request to Power-Down Mode) (PCIPWDWN):
The power state D3 (PWRS_D3) bit of the PCI power management interrupt register (PCIPINT) is
set. The power state D3 interrupt mask can be set using the power state D3 (PWRS_D3) bit of the
PCI power management interrupt mask register (PCIPINTM).
22.6.2 Interrupts from External PCI Devices
To receive interrupt signals from external PCI devices, etc., while the PCIC is operating as the
host device, use the ,5/ [3:0] pin. The PCIC has no dedicated external interrupt input pin.
22.6.3 ,17$
When the PCIC is operating as a non-host device, the ,17$ output can be used for interrupts to
the host device. ,17$ can be asserted (Low output)/negated (High output) using the ,17$ output
soft control bit (INTA) of the PCI control register (PCICR). ,17$ is open collector output.
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