HD6417751 Datasheet, PDF (674/1105 Pages) Renesas Technology Corp – SuperH RISC engine

• Four interrupt sources
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently.
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
• Modem control functions (#%$ and %$) are provided.
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
the receive data in the receive FIFO register, can be ascertained.
• A timeout error (DR) can be detected during reception.
Rev. 3.0, 04/02, page 634 of 1064