HD6417751 Datasheet, PDF (337/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 5: UNIE
0
1
Description
Interrupt due to underflow (TUNI) is not enabled
Interrupt due to underflow (TUNI) is enabled
(Initial value)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): In channels 0 to 2, these bits select the
external clock input edge when an external clock is selected or the input capture function is used.
Bit 4: CKEG1 Bit 3: CKEG0
0
0
1
1
X
Note: X: 0 or 1 (don’t care)
Description
Count/input capture register set on rising edge (Initial value)
Count/input capture register set on falling edge
Count/input capture register set on both rising and falling edges
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): In channels 0 to 2, these bits select the
TCNT count clock.
When the on-chip RTC output clock is selected as the count clock for a channel, that channel can
operate even in module standby mode. When another clock is selected, the channel does not
operate in standby mode.
Bit 2: TPSC2
0
1
Bit 1: TPSC1
0
1
0
1
Bit 0: TPSC0
0
1
0
1
0
1
0
1
Description
Counts on Pφ/4
(Initial value)
Counts on Pφ/16
Counts on Pφ/64
Counts on Pφ/256
Counts on Pφ/1024
Reserved (Do not set)
Counts on on-chip RTC output clock (Do not
set in channels 3 and 4)
Counts on external clock (Do not set in
channels 3 and 4)
12.2.7 Input Capture Register (TCPR2)
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in
channel 2.
The input capture function is controlled by means of the input capture control bits (ICPE1, ICPE0)
and clock edge bits (CKEG1, CKEG0) in TCR2. When input capture occurs, the TCNT2 value is
copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
Rev. 3.0, 04/02, page 297 of 1064