HD6417751 Datasheet, PDF (908/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 31 to 24—Memory Space Base Address (MBR31 to 24): Sets the base address for the PCI
memory space in PIO transfers. (Initial value is undefined.)
Bits 23 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 0—Lock Transfer (LOCK): Specifies the locking of the memory space during PIO transfer.
Bit 0: LOCK
0
1
Description
Not locked
Locked
(Initial value)
22.2.34 I/O Space Base Register (PCIIOBR)
Bit: 31
30
29
28
27
26
25
24
IOBR31 IOBR30 IOBR29 IOBR28 IOBR27 IOBR26 IOBR25 IOBR24
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
IOBR23 IOBR22 IOBR21 IOBR20 IOBR19 IOBR18 —
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
LOCK
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R/W
Rev. 3.0, 04/02, page 868 of 1064