HD6417751 Datasheet, PDF (948/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Address/Data Stepping Timing: By writing 1 to the WCC bit (bit 7 of the PCICONF1), a wait
(stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the
PCIC drives the AD bus over 2 clocks. This function can be used when there is a heavy load on
the PCI bus and the AD bus does not achieve the stipulated logic level in one clock.
When the PCIC operates as the host, it is recommended to use this function for the issuance of
configuration transfers.
Figure 22.15 is an example of burst memory write cycle with stepping. Figure 22.16 is an example
of target burst read cycle with stepping.
PCICLK
AD31–AD0
PAR
C/ –C/
Addr
D0
AP
DP0
Com
BE0
Dn
DPn-1
DPn
BEn
Addr: PCI space address
Dn: nth data
AP: Address parity
DPn: nth data parity
Com: Command
BEn: nth data byte enable
Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping)
Rev. 3.0, 04/02, page 908 of 1064