HD6417751 Datasheet, PDF (1008/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D31–D0
(read)
D31–D0
(write)
T1
T2
t_AD
t_CSD
t_RWD
t_AD
t_CSD
t_RWD
t_RSD
t_RSD
t_RSD
t_RDS
t_RDH
t_{WED1 tWEDF}
t_WEDF
t_WDD
t_WDD
t_WDD
t_BSD
t_BSD
DACKn
(SA: IO ← memory)
t_DACD
DACKn
(SA: IO → memory)
t_DACDF
t_DACD
t_DACD
t_DACDF
DACKn
(DA)
t_DACD
t_DACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Rev. 3.0, 04/02, page 968 of 1064