HD6417751 Datasheet, PDF (14/1105 Pages) Renesas Technology Corp – SuperH RISC engine

13.2.11 Refresh Timer Control/Status Register (RTCSR).............................................. 354
13.2.12 Refresh Timer Counter (RTCNT) .................................................................... 356
13.2.13 Refresh Time Constant Register (RTCOR)....................................................... 357
13.2.14 Refresh Count Register (RFCR)....................................................................... 358
13.2.15 Notes on Accessing Refresh Control Registers ................................................. 358
13.3 Operation..................................................................................................................... 359
13.3.1 Endian/Access Size and Data Alignment.......................................................... 359
13.3.2 Areas............................................................................................................... 366
13.3.3 SRAM Interface .............................................................................................. 370
13.3.4 DRAM Interface.............................................................................................. 378
13.3.5 Synchronous DRAM Interface ......................................................................... 393
13.3.6 Burst ROM Interface ....................................................................................... 419
13.3.7 PCMCIA Interface .......................................................................................... 422
13.3.8 MPX Interface................................................................................................. 433
13.3.9 Byte Control SRAM Interface.......................................................................... 451
13.3.10 Waits between Access Cycles .......................................................................... 455
13.3.11 Bus Arbitration................................................................................................ 457
13.3.12 Master Mode ................................................................................................... 460
13.3.13 Slave Mode ..................................................................................................... 461
13.3.14 Cooperation between Master and Slave............................................................ 461
13.3.15 Notes on Usage ............................................................................................... 462
Section 14 Direct Memory Access Controller (DMAC)........................................ 463
14.1 Overview..................................................................................................................... 463
14.1.1 Features........................................................................................................... 463
14.1.2 Block Diagram (SH7751) ................................................................................ 466
14.1.3 Pin Configuration (SH7751) ............................................................................ 467
14.1.4 Register Configuration (SH7751)..................................................................... 468
14.2 Register Descriptions ................................................................................................... 470
14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................ 470
14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)................................ 471
14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ....................... 472
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................. 473
14.2.5 DMA Operation Register (DMAOR) ............................................................... 481
14.3 Operation..................................................................................................................... 483
14.3.1 DMA Transfer Procedure ................................................................................ 483
14.3.2 DMA Transfer Requests .................................................................................. 486
14.3.3 Channel Priorities............................................................................................ 490
14.3.4 Types of DMA Transfer .................................................................................. 493
14.3.5 Number of Bus Cycle States and '5(4 Pin Sampling Timing ......................... 502
14.3.6 Ending DMA Transfer..................................................................................... 516
14.4 Examples of Use .......................................................................................................... 519
Rev. 3.0, 04/02, page xii of xxxviii