HD6417751 Datasheet, PDF (943/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Target Read/Write Cycle Timing: The PCIC responds to target memory read accesses from an
external master by retries until 8 longword data are prepared in the PCIC's internal FIFO. That is,
it always responds to the first target read with a retry.
Also, if a target memory write access is made, the PCIC responds to all subsequent target memory
accesses with a retry until the write data is completely written to local memory. Thus, the content
of the data is guaranteed when data written to the target is immediately subject to a target read
operation.
The following restrictions apply to the SH7751.
In a system in which access is made to the same address in local memory by two or more PCI
devices, the data cannot be guaranteed when a target read is performed immediately after a target
write.
The possibility of an error occurs when the target read immediately after the target write gets bus
privileges at the point the data is ready for a target read by a different PCI device prior to the
target write. In this case, the data prior to the target write is read. If such transfers are likely to
occur, implement either (a) or (b) below.
(a) If using the data that has been read, perform two read operations and use only the data from the
second read operation.
(b) If not using the data that has been read (if you are performing the read operation in order to
determine the timing for actually writing data to the destination), be sure that the read address*
immediately after writing is different from the write address.
Note: * The address that does not correspond to the address AD[31:2] on a longword boundary.
With the SH7751R, in the following case the values of data are discarded for a target read that is
executed immediately after a target write because the data read in an earlier read operation that
was carried out by a different PCI device are discarded.
Only single transfers are supported in the case of target accesses of the configuration space and
I/O space. If there is a burst access request, the external master is disconnected on completion of
the first transfer.
Note that the '(96(/ response speed is fixed at 2 clocks (Medium) in the case of target access of
the PCIC.
Figure 22.11 shows an example target single read cycle in non-host mode. Figure 22.12 shows an
example target single write cycle in non-host mode. Figure 22.13 is an example of a target burst
read cycle in host mode. And Figure 22.14 is an example target burst write cycle in host mode.
Rev. 3.0, 04/02, page 903 of 1064