HD6417751 Datasheet, PDF (20/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.21 PCI Interrupt Mask Register (PCIINTM) ......................................................... 848
22.2.22 PCI Address Data Register at Error (PCIALR)................................................. 850
22.2.23 PCI Command Data Register at Error (PCICLR).............................................. 851
22.2.24 PCI Arbiter Interrupt Register (PCIAINT) ....................................................... 853
22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM)........................................... 855
22.2.26 PCI Error Bus Master Data Register (PCIBMLR) ............................................ 856
22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT).................................... 857
22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0])....................... 858
22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0])..... 859
22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]).............................. 860
22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0])............................................ 862
22.2.32 PIO Address Register (PCIPAR)...................................................................... 865
22.2.33 Memory Space Base Register (PCIMBR)......................................................... 867
22.2.34 I/O Space Base Register (PCIIOBR) ................................................................ 868
22.2.35 PCI Power Management Interrupt Register (PCIPINT)..................................... 870
22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM)........................ 871
22.2.37 PCI Clock Control Register (PCICLKR).......................................................... 872
22.2.38 PCIC-BSC Registers........................................................................................ 873
22.2.39 Port Control Register (PCIPCTR) .................................................................... 874
22.2.40 Port Data Register (PCIPDTR) ........................................................................ 877
22.2.41 PIO Data Register (PCIPDR)........................................................................... 878
22.3 Description of Operation.............................................................................................. 879
22.3.1 Operating Modes ............................................................................................. 879
22.3.2 PCI Commands ............................................................................................... 880
22.3.3 PCIC Initialization........................................................................................... 881
22.3.4 Local Register Access...................................................................................... 882
22.3.5 Host Functions ................................................................................................ 882
22.3.6 PCI Bus Arbitration in Non-host Mode ............................................................ 885
22.3.7 PIO Transfers .................................................................................................. 885
22.3.8 Target Transfers .............................................................................................. 888
22.3.9 DMA Transfers ............................................................................................... 891
22.3.10 Transfer Contention within PCIC..................................................................... 897
22.3.11 PCI Bus Basic Interface ................................................................................... 898
22.4 Endians........................................................................................................................ 910
22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules ........................ 910
22.4.2 Endian Control for Local Bus .......................................................................... 912
22.4.3 Endian Control in DMA Transfers ................................................................... 912
22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write) ................. 914
22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write) ................................. 917
22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write). 917
22.5 Resetting...................................................................................................................... 919
22.6 Interrupts ..................................................................................................................... 920
22.6.1 Interrupts from PCIC to CPU........................................................................... 920
Rev. 3.0, 04/02, page xviii of xxxviii