HD6417751 Datasheet, PDF (352/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 13.3 External Memory Space Map
Area
External
Addresses
Size
Connectable
Memory
Settable Bus
Widths
Access Size
0
H'00000000– 64 Mbytes SRAM
H'03FFFFFF
Burst ROM
MPX
8, 16, 32*¹
8, 16, 32*¹
32*¹
8, 16, 32,
64*⁶ bits,
32 bytes
1
H'04000000– 64 Mbytes SRAM
8, 16, 32*²
8, 16, 32,
H'07FFFFFF
MPX
32*²
Byte control SRAM 16, 32*²
64*⁶ bits,
32 bytes
2
H'08000000– 64 Mbytes SRAM
8, 16, 32*²
8, 16, 32,
H'0BFFFFFF
Synchronous DRAM 32*^2,*³
MPX
32*²
64*⁶ bits,
32 bytes
3
H'0C000000– 64 Mbytes SRAM
8, 16, 32*²
8, 16, 32,
H'0FFFFFFF
Synchronous DRAM 32*^2,*³
DRAM
16, 32*^2,*³
64*⁶ bits,
32 bytes
MPX
32*²
4
H'10000000– 64 Mbytes SRAM
8, 16, 32*²
8, 16, 32,
H'13FFFFFF
MPX
Byte control RAM
32*²
16, 32*²
64*⁶ bits,
32 bytes
5
H'14000000– 64 Mbytes SRAM
H'17FFFFFF
MPX
Burst ROM
PCMCIA
8, 16, 32*²
32*²
8, 16, 32*²
8, 16*^2,*⁴
8, 16, 32,
64*⁶ bits,
32 bytes
6
H'18000000– 64 Mbytes SRAM
H'1BFFFFFF
MPX
Burst ROM
8, 16, 32*²
32*²
8,16, 32*²
8, 16, 32,
64*⁶ bits,
32 bytes
PCMCIA
8,16*^2,*⁴
7*⁵
H'1C000000– 64 Mbytes —
—
H'1FFFFFFF
Notes: *1 Memory bus width specified by external pins
*2 Memory bus width specified by register
*3 With synchronous DRAM interface, bus width is 32 bits only
With DRAM interface, bus width is 16 or 32 bits only
*4 With PCMCIA interface, bus width is 8 or 16 bits only
*5 Do not access a reserved area, as operation cannot be guaranteed in this case
*6 A 64-bit access size applies only to transfer by the DMAC (CHCRn.TS = 000).
In the case of access to external memory by means of FMOV (FPSCR.SZ = 1), two
32-bit access size transfers are performed.
Rev. 3.0, 04/02, page 312 of 1064