HD6417751 Datasheet, PDF (924/1105 Pages) Renesas Technology Corp – SuperH RISC engine

1. Initial order of priority
(transfer by device 1)
PCIC > device 1 > device 2 > device 3 > device 4
2. Order of priority after transfer PCIC > device 2 > device 3 > device 4 > device 1
(transfer by PCIC)
3. Order of priority after transfer device 2 > device 3 > device 4 > device 1 > PCIC
(transfer by device 3)
4. Order of priority after transfer device 2 > device 4 > device 1 > PCIC > device 3
When the PCIC is operating as the host device, the PCIC performs the PCI bus parking (bus
drive when not in use).
When 3 or fewer master devices are connected, set the level of the unused pins of 3&,5(4
[4:1] high.
In non-host mode, the PCI bus arbitration function of the PCIC is disabled. PCI bus arbitration
is performed according to the specifications of the connected PCI bus arbiter. For details, see
section 22.3.6, PCI Bus Arbitration in Non-host Mode.
Configuration Register Access: The configuration register of external PCI devices can be
accessed when the PCIC is operating as the host device. The PIO address register (PCIPAR) and
PIO data register (PCIPDR) are used to generate a configuration read/write transfer for accessing
the configuration register.
The PCIC supports the configuration mechanism stipulated in the PCI local bus spec.
First, specify in the PCIPAR the address of the configuration register of the external PCI device to
be accessed. See section 22.2, PCIC Register Descriptions, for how to set the PCIPAR.
Next, read data from the PCIPDR or write data to the PCIPDR. Only longword (32-bit) access of
the PCIPDR is supported.
Special Cycle Generation: When the PCIC operates as the host device, a special cycle is
generated by setting H'8000FF00 in the PCIPAR and writing to the PCIPDR.
Reset Output: When the PCIC is operating as the host device, 3&,567 can be used to reset the
PCI bus. See section 22.5, Resetting, for details of 3&,567.
Clock Output: When the PCIC is operating as the host device and the bus clock (CKIO pin) is
selected as the PCI bus clock, not only does the PCIC’s PCI bus clock operate using the CKIO
clock but the CKIO clock can also be used as the PCI bus clock. Thus, there is no requirement for
an external PCI clock oscillation circuit.
When using the CKIO clock, please note the limitations on CKIO clock frequency, stability, and
load capacitance that can be connected to the CKIO pin. Check the clock oscillation circuit and
Rev. 3.0, 04/02, page 884 of 1064