HD6417751 Datasheet, PDF (781/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit: 15
14
13
12
11
10
9
8
Bit name: NMIL MAI
—
—
—
—
NMIB NMIE
Initial value: 0/1*
0
0
0
0
0
0
0
R/W: R
R/W
—
—
—
—
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: IRLM
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
—
—
—
—
—
—
—
Note: * 1 when NMI pin input is high, 0 when low.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. It cannot be modified.
Bit 15: NMIL
0
1
Description
NMI pin input level is low
NMI pin input level is high
Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked
while the NMI pin input level is low, irrespective of the CPU’s SR.BL bit.
Bit 14: MAI
Description
0
Interrupts enabled even while NMI pin is low
(Initial value)
1
Interrupts disabled while NMI pin is low*
Note: * NMI interrupts are accepted in normal operation and in sleep mode.
In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is
low.
Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or
detected immediately while the SR.BL bit is set to 1.
Bit 9: NMIB
Description
0
NMI interrupt requests held pending while SR.BL bit is set to 1
(Initial value)
1
NMI interrupt requests detected while SR.BL bit is set to 1
Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information
will be lost, and so must be saved beforehand.
2. This bit is cleared automatically by NMI acceptance.
Rev. 3.0, 04/02, page 741 of 1064