HD6417751 Datasheet, PDF (365/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type
of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as
SRAM interface. DRAM and synchronous DRAM can also be directly connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
0
Areas 2 and 3 are accessed as SRAM
interface or MPX interface*
(Initial value)
1
Reserved (Cannot be set)
1
0
Area 2 is accessed as SRAM interface or
MPX interface*, area 3 is synchronous
DRAM interface
1
Areas 2 and 3 are accessed as
synchronous DRAM interface
1
0
0
Area 2 is accessed as SRAM interface or
MPX interface*, area 3 is DRAM interface
1
Reserved (Cannot be set)
1
0
Reserved (Cannot be set)
1
Reserved (Cannot be set)
Note: * Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX
bit
Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of these bits has priority over the MEMMPX and AnBST bit
settings.
Bit 0: A56PCM
Description
0
Areas 5 and 6 are accessed as SRAM interface
1
Areas 5 and 6 are accessed as PCMCIA interface*
Note: * The MD3 pin is designated for output as the &($ pin.
The MD4 pin is designated for output as the &(% pin.
(Initial value)
Rev. 3.0, 04/02, page 325 of 1064