HD6417751 Datasheet, PDF (417/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Read-Strobe Negate Timing (Setting Only Possible in the SH7751R): When the SRAM
interface is used, timing for the negation of the strobe during read operations can be specified by
the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this
setting, see the description of the WCR3 register. When a byte control SRAM setting is made,
AnRDH should be cleared to 0.
CKIO
A25–A0
TS1 T1 Tw Tw Tw Tw T2 TH1 TH2
RD/
*
RD
D31–D0
TS1: Setup wait
WCR3.AnS
(0 to 1)
Tw: Access wait
WCR2.AnW
(0 to 15)
TH1, TH2: Hold wait
WCR3.AnH
(0 to 3)
Note: * When AnRDH is set to 1
Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting)
Rev. 3.0, 04/02, page 377 of 1064