HD6417751 Datasheet, PDF (26/1105 Pages) Renesas Technology Corp – SuperH RISC engine

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MPX Interface Timing 3
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits).......................................................................... 445
MPX Interface Timing 4
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits).......................................................................... 446
MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 447
MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 448
MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 449
MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 450
Example of 52-Bit Data Width Byte Control SRAM ..................................... 451
Byte Control SRAM Basic Read Cycle (No Wait) ........................................ 452
Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ................ 453
Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait) ........................................................................................................... 454
Waits between Access Cycles....................................................................... 456
Arbitration Sequence.................................................................................... 459
Block Diagram of DMAC ............................................................................ 466
DMAC Transfer Flowchart........................................................................... 485
Round Robin Mode ...................................................................................... 491
Example of Changes in Priority Order in Round Robin Mode ....................... 492
Data Flow in Single Address Mode............................................................... 494
DMA Transfer Timing in Single Address Mode............................................ 495
Operation in Dual Address Mode.................................................................. 496
Example of Transfer Timing in Dual Address Mode ..................................... 497
Example of DMA Transfer in Cycle Steal Mode ........................................... 498
Example of DMA Transfer in Burst Mode .................................................... 498
Bus Handling with Two DMAC Channels Operating .................................... 502
Dual Address Mode/Cycle Steal Mode External Bus → External Bus/
'5(4 (Level Detection), DACK (Read Cycle) ............................................ 505
Dual Address Mode/Cycle Steal Mode External Bus → External Bus/
'5(4 (Edge Detection), DACK (Read Cycle) ............................................. 506
Dual Address Mode/Burst Mode External Bus → External Bus/
'5(4 (Level Detection), DACK (Read Cycle) ............................................ 507
Rev. 3.0, 04/02, page xxiv of xxxviii