HD6417751 Datasheet, PDF (146/1105 Pages) Renesas Technology Corp – SuperH RISC engine

the entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
3. OC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag stored in the
entry specified in the address field is compared with the tag specified in the data field. If the
MMU is enabled at this time, comparison is performed after the virtual address specified by
data field bits [31:10] has been translated to a physical address using the UTLB. If the
addresses match and the V bit is 1, the U bit and V bit specified in the data field are written
into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no
operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit,
write-back is performed. If a UTLB miss occurs during address translation, or the comparison
shows a mismatch, an exception is not generated, no operation is performed, and the write is
not executed. If a data TLB multiple hit exception occurs during address translation,
processing switches to the data TLB multiple hit exception handling routine.
31
24 23
Address field _{1 1 1 1 0 1 0 0}
14 13
Entry
31
10 9
Data field
Tag
V : Validity bit
U : Dirty bit
A : Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.10 Memory-Mapped OC Address Array
543210
A
210
UV
4.5.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is
specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification.
Address field bits [4:2] are used for the longword data specification in the entry. As only longword
access is used, 0 should be specified for address field bits [1:0].
The data field is used for the longword data specification.
Rev. 3.0, 04/02, page 106 of 1064