HD6417751 Datasheet, PDF (590/1105 Pages) Renesas Technology Corp – SuperH RISC engine

14.6 Configuration of the DMAC (SH7751R)
14.6.1 Block Diagram of the DMAC
Figure 14.53 is a block diagram of the DMAC in the SH7751R.
On-chip
peripheral
module
TMU
SCI, SCIF
DMAC module
Count control
SAR0–7
Registr control
Activation
control
DAR0–7
DMATCR0–7
CHCR0–7
Request
priority
control
DMAOR
queclr0–7
DACK0, DACK1
DRAK0, DRAK1
Bus
interface
8
Request
dreq0–7
dmaqueclr0-7
SAR0, DAR0, DMATCR0,
CHCR0 only
DDT module
,
DTR command buffer
/
D[31:0]
ID[1:0]
External bus
32B data
buffer
Bus state
controller
DMAOR: DMAC operation register
SAR:
DMAC source address register
DAR:
DMAC destination address register
DMATCR: DMAC transfer count register
CHCR: DMAC channel control register
DBREQ
DDTMODE
BAVL
DDTD
48 bits
id[2:0]
tdack
Request controller
CH0 CH1 CH2 CH3
CH4 CH5 CH6 CH7
Figure 14.53 Block Diagram of the DMAC
Rev. 3.0, 04/02, page 550 of 1064