HD6417751 Datasheet, PDF (31/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 22.19 Endian Control for Local Bus ....................................................................... 912
Figure 22.20 Data Alignment at DMA Transfer................................................................. 913
Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) ............ 915
Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus).......... 916
Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) . 917
Figure 22.23 Data Alignment at Target Configuration Transfer
(Both Big Endian and Little Endian)............................................................. 918
Figure 23.1 EXTAL Clock Input Timing......................................................................... 956
Figure 23.2(1) CKIO Clock Output Timing ......................................................................... 956
Figure 23.2(2) CKIO Clock Output Timing ......................................................................... 956
Figure 23.3 Power-On Oscillation Settling Time ............................................................. 957
Figure 23.4 Standby Return Oscillation Settling Time (Return by 5(6(7 or ) 05(6(7 .. 957
Figure 23.5 Power-On Oscillation Settling Time ............................................................. 958
Figure 23.6 Standby Return Oscillation Settling Time (Return by 5(6(7 or ) 05(6(7 .. 958
Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI) .......................... 959
Figure 23.8 Standby Return Oscillation Settling Time (Return by – ) ,5/ ,5/ ................ 959
Figure 23.9 PLL Synchronization Settling Time in Case of 5(6(7 05(6(7 or
NMI Interrupt............................................................................................... 960
Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt ........................ 960
Figure 23.11 Control Signal Timing.................................................................................. 963
Figure 23.12 Pin Drive Timing for Standby Mode ............................................................. 963
Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) ............................................. 968
Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ............................... 969
Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) 970
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
Insertion, AnS = 1, AnH = 1)........................................................................ 971
Figure 23.17 Burst ROM Bus Cycle (No Wait) ................................................................. 972
Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
2nd/3rd/4th Data: One Internal Wait)............................................................ 973
Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
AnS = 1, AnH = 1) ....................................................................................... 974
Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait)................... 975
Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle:
Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)........................ 976
Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle:
Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ......................... 977
Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Burst (RCD [1:0] = 01, CAS Latency = 3) .................................................... 978
Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3) ...... 979
Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command,
Burst (CAS Latency = 3) .............................................................................. 980
Rev. 3.0, 04/02, page xxix of xxxviii