HD6417751 Datasheet, PDF (258/1105 Pages) Renesas Technology Corp – SuperH RISC engine

9.2 Register Descriptions
9.2.1 Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the
power-down mode status. It is initialized to H'00 by a power-on reset via the 5(6(7 pin or due to
watchdog timer overflow.
Bit:
Initial value:
R/W:
7
STBY
0
R/W
6
PHZ
0
R/W
5
PPU
0
R/W
4
MSTP4
0
R/W
3
MSTP3
0
R/W
2
MSTP2
0
R/W
1
MSTP1
0
R/W
0
MSTP0
0
R/W
Bit 7—Standby (STBY): Specifies a transition to standby mode.
Bit 7: STBY
0
1
Description
Transition to sleep mode on execution of SLEEP instruction (Initial value)
Transition to standby mode on execution of SLEEP instruction
Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of
peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module
related pins go to the high-impedance state in standby mode.
For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control.
Bit 6: PHZ
0
1
Description
Peripheral module related pins are in normal state
Peripheral module related pins go to high-impedance state
(Initial value)
Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module
related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral
module related pins in the input or high-impedance state.
For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.
Bit 5: PPU
0
1
Description
Peripheral module related pin pull-up resistors are on
Peripheral module related pin pull-up resistors are off
(Initial value)
Rev. 3.0, 04/02, page 218 of 1064