HD6417751 Datasheet, PDF (24/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 12.7 Operation Timing when Using Input Capture Function ................................. 302
Figure 13.1 Block Diagram of BSC................................................................................. 307
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space 311
Figure 13.3 External Memory Space Allocation .............................................................. 313
Figure 13.4 Example of 5'< Sampling Timing at which BCR4 is Set
(Two Wait Cycles are Inserted by WCR2) .................................................... 330
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR......................................... 359
Figure 13.6 Basic Timing of SRAM Interface ................................................................. 371
Figure 13.7 Example of 32-Bit Data Width SRAM Connection ....................................... 372
Figure 13.8 Example of 16-Bit Data Width SRAM Connection ....................................... 373
Figure 13.9 Example of 8-Bit Data Width SRAM Connection ......................................... 374
Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)..................................... 375
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by 5'< Signal) .... 376
Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting) .... 377
Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3) ........................ 378
Figure 13.14 Basic DRAM Access Timing........................................................................ 380
Figure 13.15 DRAM Wait State Timing............................................................................ 381
Figure 13.16 DRAM Burst Access Timing........................................................................ 382
Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)..................... 383
Figure 13.18 Burst Access Timing in DRAM EDO Mode ................................................. 384
Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, Anw = 0) .......................................................... 385
Figure 13.19(2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, Anw = 0) .......................................................... 386
Figure 13.19(3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, Anw = 0) ................................................................. 387
Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, Anw = 0) ................................................................. 388
Figure 13.20 CAS-Before-RAS Refresh Operation............................................................ 389
Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) ....... 390
Figure 13.22 DRAM Self-Refresh Cycle Timing............................................................... 392
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... 394
Figure 13.24 Basic Timing for Synchronous DRAM Burst Read ....................................... 396
Figure 13.25 Basic Timing for Synchronous DRAM Single Read...................................... 398
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write ...................................... 399
Figure 13.27 Basic Timing for Synchronous DRAM Single Write ..................................... 401
Figure 13.28 Burst Read Timing ....................................................................................... 403
Figure 13.29 Burst Read Timing (RAS Down, Same Row Address) .................................. 404
Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses).......................... 405
Figure 13.31 Burst Write Timing ...................................................................................... 406
Figure 13.32 Burst Write Timing (Same Row Address)..................................................... 407
Figure 13.33 Burst Write Timing (Different Row Addresses) ............................................ 408
Rev. 3.0, 04/02, page xxii of xxxviii