HD6417751 Datasheet, PDF (804/1105 Pages) Renesas Technology Corp – SuperH RISC engine

In the SH7751 Series, all operand accesses are treated as either read accesses or write accesses.
The following instructions require special attention:
• PREF, OCBP, and OCBWB instructions: Treated as read accesses.
• MOVCA.L and OCBI instructions: Treated as write accesses.
• TAS.B instruction: Treated as one read access and one write access.
The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no
access data.
The SH7751 Series handles all operand accesses as having a data size. The data size can be byte,
word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L,
and OCBI instructions is treated as longword.
20.3.2 Explanation of Terms Relating to Instruction Intervals
In this section, “1 (2, 3, ...) instruction(s) after...”, as a measure of the distance between two
instructions, is defined as follows. A branch is counted as an interval of two instructions.
• Example of sequence of instructions with no branch:
100 Instruction A (0 instructions after instruction A)
102 Instruction B (1 instruction after instruction A)
104 Instruction C (2 instructions after instruction A)
106 Instruction D (3 instructions after instruction A)
• Example of sequence of instructions with a branch (however, the example of a sequence of
instructions with no branch should be applied when the branch destination of a delayed branch
instruction is the instruction itself + 4):
100 Instruction A: BT/S L200 (0 instructions after instruction A)
102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B)
L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B)
202 Instruction D (4 instructions after instruction A, 3 instructions after instruction
B)
Rev. 3.0, 04/02, page 764 of 1064