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HD6417751 Datasheet, PDF (1041/1105 Pages) Renesas Technology Corp – SuperH RISC engine
CKIO
Address
RD/
Tpc
Tr1
Tr2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
tAD
tAD
Row
c1
c2
tCSD
tRWD
tAD
c8
tCSD
tRWD
tRASD tRASD
tCASD1
tCASD1
tCASD1
tCASD1
tCASD1
D31–D0
(read)
D31–D0
(write)
tRDS
tRDH
d1
d2
tWDD
tWDD
d1
tWDD
d2
tBSD tBSD
tRDS
d8
tRDH
d8
tWDD
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
tDACD tDACD
tDACD tDACD
tDACD
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)
Rev. 3.0, 04/02, page 1001 of 1064