HD6417751 Datasheet, PDF (687/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from
SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit
trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and
new transmit data can be written to SCFTDR2.
Bit 5: TDFE
0
Description
A number of transmit data bytes exceeding the transmit trigger set number
have been written to SCFTDR2
[Clearing conditions]
• When transmit data exceeding the transmit trigger set number is written
to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE
• When transmit data exceeding the transmit trigger set number is written
to SCFTDR2 by the DMAC
1
The number of transmit data bytes in SCFTDR2 does not exceed the
transmit trigger set number
(Initial value)
[Setting conditions]
• Power-on reset or manual reset
• When the number of SCFTDR2 transmit data bytes falls to or below the
transmit trigger set number as the result of a transmit operation*
Note: * As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written
when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be
ignored.
The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2.
Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 4: BRK
0
Description
A break signal has not been received
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to BRK after reading BRK = 1
(Initial value)
1
A break signal has been received*
[Setting condition]
When data with a framing error is received, followed by the space “0” level
(low level ) for at least one frame length
Note: * When a break is detected, the receive data (H'00) following detection is not transferred to
SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive data
transfer is resumed.
Rev. 3.0, 04/02, page 647 of 1064