HD6417751 Datasheet, PDF (1055/1105 Pages) Renesas Technology Corp – SuperH RISC engine

23.3.4 Peripheral Module Signal Timing
Table 23.28 Peripheral Module Signal Timing (1)
HD6417751 HD6417751 HD6417751 HD6417751
RBP240 RBP200 RF240
RF200
*²
*²
*²
*²
Module Item
Symbol Min Max
TMU, Timer clock t_TCLKWH 4
—
RTC pulse width
(high)
Timer clock t_TCLKWL 4
—
pulse width
(low)
Timer clock t_TCLKr
rise time
— 0.8
Timer clock t_TCLKf
fall time
— 0.8
Min Max
4—
4—
— 0.8
— 0.8
Min Max
4—
4—
— 0.8
— 0.8
Min Max Unit Figure Notes
4 — Pcyc*¹ 23.64
4 — Pcyc*¹ 23.64
— 0.8 Pcyc*¹ 23.64
— 0.8 Pcyc*¹ 23.64
Oscillation t_ROSC
settling time
—3
—3
—3
—3 s
23.64
SCI
Input clock t_Scyc
cycle (asyn-
chronous)
4—
4—
4—
4 — Pcyc*¹ 23.64
Input clock t_Scyc
cycle (syn-
chronous)
6—
6—
6—
6 — Pcyc*¹ 23.64
Input clock t_SCKW
pulse width
Input clock t_SCKr
rise time
Input clock t_SCKf
fall time
0.4 0.6
— 0.8
0.4 0.6
— 0.8
0.4 0.6
— 0.8
0.4 0.6 t_Scyc 23.64
— 0.8 Pcyc*¹ 23.64
— 0.8 — 0.8 — 0.8 — 0.8 Pcyc*¹ 23.64
Transfer
t_TXD
data delay
time
1.5 5.3 1.5 5.3 1.5 6
1.5 6 ns 23.64
Receive
t_RXS
data setup
time (syn-
chronous)
16 — 16 — 16 — 16 — ns 23.64
Receive
t_RXH
data hold
time (syn-
chronous)
16 — 16 — 16 — 16 — ns 23.64
I/O
ports
Output data t_PORTD
delay time
1.5 5.3
1.5 5.3
1.5 6
1.5 6 ns 23.64
Input data t_PORTS
2
—
setup time
2.5 —
3.5 —
3.5 — ns 23.64
Input data
hold time
t_PORTH
1.5 —
1.5 —
1.5 —
1.5 — ns 23.64
Rev. 3.0, 04/02, page 1015 of 1064