HD6417751 Datasheet, PDF (441/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Tpc
Row
Row
H/L
Row
c1
D31–D0
c1
(write)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.27 Basic Timing for Synchronous DRAM Single Write
Rev. 3.0, 04/02, page 401 of 1064