HD6417751 Datasheet, PDF (1023/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Burst (RCD [1:0] = 01, TRWL [2:0] = 010)
Rev. 3.0, 04/02, page 983 of 1064