HD6417751 Datasheet, PDF (894/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits
when writing.
Bit 13—Master Broken Interrupt (MST_BRKN): Detects when the master granted with bus
privileges does not start a transaction ()5$0( not asserted) within 16 clocks.
Bit 12—Target Bus Timeout Interrupt (TGT_BUSTO): Neither 75'< nor 6723 are not
returned within 16 clocks in the case of the first data transfer, or within 8 clocks in the case of
second and subsequent data transfers.
Bit 11—Master Bus Timeout Interrupt (MST_BUSTO): ,5'< is not returned within 8 clocks.
Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 3—Target Abort Interrupt (TGT_ABORT): Indicates the termination of transaction by
target abort when a device other than the PCIC is operating as the bus master.
Bit 2—Master Abort Interrupt (MST_ABORT): Indicates the termination of transaction by
master abort when a device other than the PCIC is operating as the bus master.
Bit 1—Read Data Parity Error Interrupt (DPERR_WT): Indicates the detection of the
assertion of 3(55 in a data read operation when a device other than the PCIC is operating as the
bus master.
Bit 0—Write Data Parity Error Interrupt (DPERR_RD): Indicates the detection of the
assertion of 3(55 in a data write operation when a device other than the PCIC is operating as the
bus master.
Rev. 3.0, 04/02, page 854 of 1064