HD6417751 Datasheet, PDF (622/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in
SCRDR1.
Bit 6: RDRF
0
Description
There is no valid receive data in SCRDR1
(Initial value)
[Clearing conditions]
• Power-on reset, manual reset, standby mode, or module standby
• When 0 is written to RDRF after reading RDRF = 1
• When data in SCRDR1 is read by the DMAC
1
There is valid receive data in SCRDR1
[Setting condition]
When serial reception ends normally and receive data is transferred from
SCRSR1 to SCRDR1
Note:
SCRDR1 and the RDRF flag are not affected and retain their previous values when an error
is detected during reception or when the RE bit in SCSCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5: ORER
0
Description
Reception in progress, or reception has ended normally*¹ (Initial value)
[Clearing conditions]
• Power-on reset, manual reset, standby mode, or module standby
• When 0 is written to ORER after reading ORER = 1
1
An overrun error occurred during reception*²
[Setting condition]
When the next serial reception is completed while RDRF = 1
Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in
SCSCR1 is cleared to 0.
*2 The receive data prior to the overrun error is retained in SCRDR1, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1. In synchronous mode, serial transmission cannot be continued either.
Rev. 3.0, 04/02, page 582 of 1064