HD6417751 Datasheet, PDF (604/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 14.18 DTR Format for Clearing Request Queues
DMAOR.DBL DTR.ID DTR.MD DTR.SZ DTR.COUNT[7:4] Description
0
00
10
110
*
Clear the request queues of all channels
(1–7).
Clear the CH0 request-accepted flag
11
Setting prohibited
1
00
10
110
*
Clear the request queues of all channels
(1–7).
Clear the CH0 request-accepted flag.
11
0001
Clear the CH0 request-accepted flag
0010
Clear the CH1 request queues.
0011
Clear the CH2 request queues.
0100
Clear the CH3 request queues.
0101
Clear the CH4 request queues.
0110
Clear the CH5 request queues.
0111
Clear the CH6 request queues.
1000
Clear the CH7 request queues.
Note: (SH7751R) DTR.SZ = DTR[31:29], DTR.ID = DTR[27:26], DTR.MD = DTR[25:24],
DTR.COUNT[7:4] = DTR[23:20]
14.8.5 Interrupt-Request Codes
When the number of transfers specified in DMATCR has been finished and the interrupt request is
enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each
channel. Table 14.19 lists the interrupt-request codes that are associated with these transfer-end
interrupts.
Rev. 3.0, 04/02, page 564 of 1064