HD6417751 Datasheet, PDF (959/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.5 Resetting
This section describes the resetting supported by the PCIC.
Power-On Reset when Host: A reset (3&,567) can be output to the PCI bus when the PCIC is
host. The 3&,567 pin is asserted when a power-on reset is generated at the 5(6(7 pin or when a
software reset is generated by setting 1 in the 3&,567 output control bit (RSTCTL) of the PCI
control register (PCICR).
Reset Input in Non-Host Mode: The PCIC has no dedicated reset input pin. A reset signal from
the PCI bus can be connected to the 5(6(7 pin and a power-on reset applied to the
SH7751/SH7751R, but the following point must be noted:
In the PCI standard, the reset (567 signal must be asserted for a minimum of 1msec, check the
time required for the power-on reset of the SH7751/SH7751R (see section 23, Electrical
Characteristics), and design the timing of power-on resets so that it satisfies the conditions of the
reset period for both.
Manual Reset: The PCIC does not support the input of manual reset signals via the 05(6(7 pin.
No initialization therefore occurs by manual resets.
Software Reset: Software resets are generated by setting 1 in the 3&,567 output control bit
(RSTCTL) of the PCI control register (PCICR). The 3&,567 pin is asserted at the same time as
the PCIC is reset. While a software reset is asserted, the PCIC registers cannot be accessed.
Assertion requires a minimum of 1ms. Software resets are canceled by setting a 0 to the RSTCTL
bit.
It is not possible to set 0 in the RSTCTL bit and set other bits of the PCICR at the same time.
After setting 0 in the RSTCTL bit, set other bits of the PCICR.
Note that not all PCIC registers are reset at a software reset. See section 22.2, PCIC Register
Descriptions, for details of which registers are reset. Use software clears as required for any
registers that are not cleared by the software reset.
Note that, since software resets cannot be asserted while the PCI bus clock is stopped, software
resets must be asserted when the PCI bus clock (PCICLK or CKIO) is being input.
Note that data cannot be guaranteed if a software reset is used while a data transfer is in progress.
Rev. 3.0, 04/02, page 919 of 1064