HD6417751 Datasheet, PDF (376/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait
states to be inserted for area 5. For the case where an MPX interface setting is made, see table
13.7.
Bit 25: A5W2
0
1
Bit 24: A5W1
0
1
0
1
Bit 23: A5W0
0
1
0
1
0
1
0
1
Description
First Cycle
Inserted Wait States
5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Bit 22: A5B2
0
1
Bit 21: A5B1
0
1
0
1
Bit 20: A5B0
0
1
0
1
0
1
0
1
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted from
Second Data Access Onward
5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
4
Enabled
5
Enabled
6
Enabled
7 (Initial value)
Enabled
Rev. 3.0, 04/02, page 336 of 1064